Invention Grant
- Patent Title: Integrated circuit combination of a target integrated circuit and a plurality of cells connected thereto using the top conductive layer
- Patent Title (中): 使用顶部导电层的目标集成电路和与其连接的多个单元的集成电路组合
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Application No.: US13270869Application Date: 2011-10-11
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Publication No.: US08952473B2Publication Date: 2015-02-10
- Inventor: Shani Keysar , Reuven Holzer , Ofer Navon , Rami Friedlander
- Applicant: Shani Keysar , Reuven Holzer , Ofer Navon , Rami Friedlander
- Applicant Address: IL Haifa
- Assignee: Sol Chip Ltd.
- Current Assignee: Sol Chip Ltd.
- Current Assignee Address: IL Haifa
- Agency: M&B IP Analysts, LLC
- Main IPC: H01L27/14
- IPC: H01L27/14 ; H01L25/16 ; H01L31/0392

Abstract:
A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.
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Information query
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