Invention Grant
- Patent Title: Stacked multi-chip bottom source semiconductor device and preparation method thereof
- Patent Title (中): 堆叠多芯片底源半导体器件及其制备方法
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Application No.: US14031283Application Date: 2013-09-19
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Publication No.: US08952509B1Publication Date: 2015-02-10
- Inventor: Hamza Yilmaz , Yueh-Se Ho , Yan Xun Xue , Jun Lu , Xiaotian Zhang , Zhi Qiang Niu , Ming-Chen Lu , Liang Zhao , YuPing Gong , GuoFeng Lian
- Applicant: Hamza Yilmaz , Yueh-Se Ho , Yan Xun Xue , Jun Lu , Xiaotian Zhang , Zhi Qiang Niu , Ming-Chen Lu , Liang Zhao , YuPing Gong , GuoFeng Lian
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: CH Emily LLC
- Agent Chein-Hwa Tsao
- Main IPC: H01L25/07
- IPC: H01L25/07 ; H01L23/495 ; H01L25/00

Abstract:
The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.
Information query
IPC分类: