Invention Grant
- Patent Title: Method for dicing a semiconductor wafer having through silicon vias and resultant structures
- Patent Title (中): 用于通过硅通孔和所得结构切割半导体晶片的方法
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Application No.: US13676888Application Date: 2012-11-14
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Publication No.: US08952542B2Publication Date: 2015-02-10
- Inventor: Pei Hsing Hua , Hui-Shan Chang
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW
- Agency: Morgan Law Offices, PLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L21/78 ; H01L23/00 ; H01L21/768

Abstract:
The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured.
Public/Granted literature
- US20140131876A1 METHOD FOR DICING A SEMICONDUCTOR WAFER HAVING THROUGH SILICON VIAS AND RESULTANT STRUCTURES Public/Granted day:2014-05-15
Information query
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