Invention Grant
- Patent Title: Memory with termination circuit
- Patent Title (中): 内存带终端电路
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Application No.: US14031462Application Date: 2013-09-19
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Publication No.: US08952719B2Publication Date: 2015-02-10
- Inventor: Masayasu Komyo , Yoichi Iizuka
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2009-206881 20090908
- Main IPC: H03K19/003
- IPC: H03K19/003 ; H03K17/16 ; G11C7/02 ; H03K19/00 ; H03K19/0175 ; G11C11/419

Abstract:
Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
Public/Granted literature
- US20140016401A1 MEMORY WITH TERMINATION CIRCUIT Public/Granted day:2014-01-16
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