Invention Grant
- Patent Title: Methods and systems for calibration of a delay locked loop
- Patent Title (中): 用于校准延迟锁定环路的方法和系统
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Application No.: US14065754Application Date: 2013-10-29
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Publication No.: US08952737B2Publication Date: 2015-02-10
- Inventor: Kishore Mishra , Purna C. Mohanty , Venkata N. S. N. Rao
- Applicant: Kool Chip, Inc.
- Applicant Address: US CA San Jose
- Assignee: Kool Chip, Inc.
- Current Assignee: Kool Chip, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Venture Pacific Law, PC
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/00

Abstract:
A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.
Public/Granted literature
- US20140312946A1 Methods and Systems for Calibration of a Delay Locked Loop Public/Granted day:2014-10-23
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