Invention Grant
US08953149B2 CMOS three-dimensional image sensor detectors having reduced inter-gate capacitance, and enhanced modulation contrast
有权
CMOS三维图像传感器检测器具有减小的栅极间电容和增强的调制对比度
- Patent Title: CMOS three-dimensional image sensor detectors having reduced inter-gate capacitance, and enhanced modulation contrast
- Patent Title (中): CMOS三维图像传感器检测器具有减小的栅极间电容和增强的调制对比度
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Application No.: US12658806Application Date: 2010-02-16
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Publication No.: US08953149B2Publication Date: 2015-02-10
- Inventor: Cyrus Bamji
- Applicant: Cyrus Bamji
- Applicant Address: US WA Redmond
- Assignee: Microsoft Corporation
- Current Assignee: Microsoft Corporation
- Current Assignee Address: US WA Redmond
- Agent Gregg Wisdom; Ramesh Kuchibhatla; Micky Minhas
- Main IPC: G01C3/08
- IPC: G01C3/08

Abstract:
A CMOS detector with pairs of interdigitated elongated finger-like collection gates includes p+ implanted regions that create charge barrier regions that can intentionally be overcome. These regions steer charge to a desired collection gate pair for collection. The p+ implanted regions may be formed before and/or after formation of the collection gates. These regions form charge barrier regions when an associated collection gate is biased low. The barriers are overcome when an associated collection gate is high. These barrier regions steer substantially all charge to collection gates that are biased high, enhancing modulation contrast. Advantageously, the resultant structure has reduced power requirements in that inter-gate capacitance is reduced in that inter-gate spacing can be increased over prior art gate spacing and lower swing voltages may be used. Also higher modulation contrast is achieved in that the charge collection area of the low gate(s) is significantly reduced.
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