Invention Grant
- Patent Title: Memory dies, stacked memories, memory devices and methods
- Patent Title (中): 存储器模块,堆叠存储器,存储器件和方法
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Application No.: US14270638Application Date: 2014-05-06
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Publication No.: US08953355B2Publication Date: 2015-02-10
- Inventor: Takuya Nakanishi , Yutaka Ito
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: G11C5/00
- IPC: G11C5/00 ; G11C7/00 ; G11C8/00 ; G11C5/02 ; G11C7/20 ; H01L25/065 ; G11C5/14 ; H01L23/48

Abstract:
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.
Public/Granted literature
- US20140241022A1 MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS Public/Granted day:2014-08-28
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