Invention Grant
US08953363B2 Nonvolatile semiconductor memory device and read method for the same
有权
非易失性半导体存储器件及其读取方法相同
- Patent Title: Nonvolatile semiconductor memory device and read method for the same
- Patent Title (中): 非易失性半导体存储器件及其读取方法相同
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Application No.: US13700329Application Date: 2012-07-11
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Publication No.: US08953363B2Publication Date: 2015-02-10
- Inventor: Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
- Applicant: Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
- Applicant Address: JP Osaka
- Assignee: Panasonic Intellectural Property Management Co., Ltd.
- Current Assignee: Panasonic Intellectural Property Management Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, LLP
- Priority: JP2011-160378 20110721
- International Application: PCT/JP2012/004493 WO 20120711
- International Announcement: WO2013/011669 WO 20130124
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C13/00 ; G11C11/16 ; G11C7/14

Abstract:
A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.
Public/Granted literature
- US20130148406A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD FOR THE SAME Public/Granted day:2013-06-13
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