Invention Grant
- Patent Title: Chained programming language preprocessors for circuit simulation
- Patent Title (中): 用于电路仿真的链式编程语言预处理器
-
Application No.: US13270052Application Date: 2011-10-10
-
Publication No.: US08954307B1Publication Date: 2015-02-10
- Inventor: Donald J. O'Riordan , Richard J. O'Donovan
- Applicant: Donald J. O'Riordan , Richard J. O'Donovan
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A netlist description that includes embedded code segments for describing a circuit is preprocessed in order to replace the embedded code segments with corresponding preprocessed code segments, where the preprocessed code segments include netlist code that can be parsed and executed. To perform this preprocessing, programming languages that include scripting operations are identified for the embedded code segments in the netlist description. A pipeline preprocessor that includes preprocessors for the identified programming languages is configured to sequentially process the netlist description and replace the embedded code segments with the corresponding preprocessed code segments.
Information query