Invention Grant
US08954714B2 Processor with cycle offsets and delay lines to allow scheduling of instructions through time
有权
具有循环偏移和延迟线的处理器，以允许通过时间调度指令
- Patent Title: Processor with cycle offsets and delay lines to allow scheduling of instructions through time
- Patent Title (中): 具有循环偏移和延迟线的处理器，以允许通过时间调度指令
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Application No.: US12698088Application Date: 2010-02-01
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Publication No.: US08954714B2Publication Date: 2015-02-10
- Inventor: Steven Perry
- Applicant: Steven Perry
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Law Offices of Maximilian R. Peterson
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38
Abstract:
An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than the set of instructions in the first memory. An instruction in the set of instructions in the first memory is used as a pointer to a corresponding instruction in the set of instructions in the second memory.
Public/Granted literature
- US20110213948A1 Efficient Processor Apparatus and Associated Methods Public/Granted day:2011-09-01
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