Invention Grant
- Patent Title: Half width counting leading zero circuit using comparators
- Patent Title (中): 使用比较器的半宽度计数引导零电路
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Application No.: US13489551Application Date: 2012-06-06
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Publication No.: US08954833B2Publication Date: 2015-02-10
- Inventor: Deepak K. Singh
- Applicant: Deepak K. Singh
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent H. Daniel Schnurmann; Arnold Bangali
- Main IPC: G06F3/048
- IPC: G06F3/048

Abstract:
An approach for determining a value representing the number of leading zero count value in a binary input data word, is described. The binary input data word contains random data. The binary input data word is logically divided into odd and even bit positions. The approach includes a first comparator circuit for comparing data in the odd bit positions to data in the even bit positions. The approach further includes a second comparator circuit for comparing the data in the odd bit positions to a result of a logical operation performed on the data in the odd and even bit positions. The approach further includes a half-width leading zero counting circuit that provides a value representing the number of leading zero bits in the binary input data word.
Public/Granted literature
- US20130332788A1 HALF WIDTH COUNTING LEADING ZERO CIRCUIT USING COMPARATORS Public/Granted day:2013-12-12
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