Invention Grant
- Patent Title: Block emulation techniques in integrated circuits
- Patent Title (中): 集成电路中的块仿真技术
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Application No.: US13850244Application Date: 2013-03-25
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Publication No.: US08954907B1Publication Date: 2015-02-10
- Inventor: Syamsul Hani Hasran , Ian Eu Meng Chan , Wai Loon Ho , Lee Shyuan Heng , Min Meng Loo , Mohd Yusuf Abdul Hamid
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble, Carlyle, Sandridge & Rice
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
Techniques for emulating a logic block in an integrated circuit (IC) design are provided. The techniques include identifying a plurality of logic elements that are connectable to formal logic block. These logic elements are connected to perform logic functions associated with the logic block. The logic block may be a physical logic block on one IC design and a non-existent logic block on another IC design. The logic elements and associated connections form an emulated logic block.
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