Invention Grant
US08954912B2 Structured placement of latches/flip-flops to minimize clock power in high-performance designs
有权
锁存器/触发器的结构化放置,以最大限度地减少高性能设计中的时钟功率
- Patent Title: Structured placement of latches/flip-flops to minimize clock power in high-performance designs
- Patent Title (中): 锁存器/触发器的结构化放置,以最大限度地减少高性能设计中的时钟功率
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Application No.: US13689437Application Date: 2012-11-29
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Publication No.: US08954912B2Publication Date: 2015-02-10
- Inventor: Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Steven L. Bennett; Jack V. Musgrove
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.
Public/Granted literature
- US20140149957A1 STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS Public/Granted day:2014-05-29
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