Invention Grant
- Patent Title: Method and system for performing fast electrical analysis and simulation of an electronic design for power gates
- Patent Title (中): 用于执行电力门电子设计的快速电气分析和仿真的方法和系统
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Application No.: US14050269Application Date: 2013-10-09
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Publication No.: US08954917B1Publication Date: 2015-02-10
- Inventor: John Yanjiang Shu , Wei Michael Tian , An-Chang Deng
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes. In some embodiments, multiple adjacent devices as identified as interface devices for purposes of the analysis. One situation where it may be useful to analyze a larger portion of the circuitry in this way where the analysis is being performed on a netlist having a power gate.
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