Invention Grant
- Patent Title: Wafer level package resistance monitor scheme
- Patent Title (中): 晶圆级封装电阻监测方案
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Application No.: US13477313Application Date: 2012-05-22
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Publication No.: US08957694B2Publication Date: 2015-02-17
- Inventor: Kunzhong Hu , Chonghua Zhong , Edward Law
- Applicant: Kunzhong Hu , Chonghua Zhong , Edward Law
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Brinks Gilson & Lione
- Main IPC: G01R31/26
- IPC: G01R31/26
Abstract:
An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.
Public/Granted literature
- US20130314120A1 WAFER LEVEL PACKAGE RESISTANCE MONITOR SCHEME Public/Granted day:2013-11-28
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