Invention Grant
- Patent Title: Phase-locked loop (PLL) circuit and communication apparatus
- Patent Title (中): 锁相环(PLL)电路和通信装置
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Application No.: US13872752Application Date: 2013-04-29
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Publication No.: US08957735B2Publication Date: 2015-02-17
- Inventor: Akihide Sai
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz, Goodman & Chick PC
- Priority: JP2012-135752 20120615
- Main IPC: H03L1/00
- IPC: H03L1/00 ; H03L7/08 ; H03L7/099

Abstract:
According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.
Public/Granted literature
- US20130335150A1 PHASE-LOCKED LOOP (PLL) CIRCUIT AND COMMUNICATION APPARATUS Public/Granted day:2013-12-19
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