Invention Grant
- Patent Title: Multiple well drain engineering for HV MOS devices
- Patent Title (中): 用于HV MOS器件的多个漏极工程
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Application No.: US13554890Application Date: 2012-07-20
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Publication No.: US08962397B2Publication Date: 2015-02-24
- Inventor: Gregory Dix , Leighton E. McKeen , Ian Livingston , Roger Melcher , Rohan Braithwaite
- Applicant: Gregory Dix , Leighton E. McKeen , Ian Livingston , Roger Melcher , Rohan Braithwaite
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Agency: King & Spalding L.L.P.
- Main IPC: H01L21/332
- IPC: H01L21/332 ; H01L21/335 ; H01L21/00 ; H01L21/8238 ; H01L21/336 ; H01L29/78 ; H01L23/544 ; H01L29/66 ; H01L29/08 ; H01L29/423
Abstract:
At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
Public/Granted literature
- US20130026545A1 MULTIPLE WELL DRAIN ENGINEERING FOR HV MOS DEVICES Public/Granted day:2013-01-31
Information query
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