According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first direction, a third conductive line extending in a third direction intersect with the first and second directions, an insulating layer disposed between the second conductive lines and the third conductive line, resistance change elements each disposed on one of first and second surfaces of each of the second conductive lines in the third direction, and each connected to the third conductive line, a semiconductor layer connected between the first conductive line and one end of the third conductive line, and a select FET having a select gate electrode, and using the semiconductor layer as a channel.