The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. The two gates logical circuit performs a logical operating on the clock enable signal, the specific mode signal and the delayed clock output signal for generating a mode selecting signal. The buffer generates a feedback signal according to the mode selecting signal and a control signal. The clock input buffer decides whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal. The delay lock loop circuit generates the delayed clock output signal. A frequency of the feedback signal is adjusted according to the control signal.