Invention Grant
- Patent Title: Integrating optimal planar and three-dimensional semiconductor design layouts
- Patent Title (中): 整合最优平面和三维半导体设计布局
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Application No.: US13792946Application Date: 2013-03-11
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Publication No.: US08966423B2Publication Date: 2015-02-24
- Inventor: Navneet Jain , Yunfei Deng , Mahbub Rashed , David Doman , Qi Xiang , Jongwook Kye
- Applicant: GLOBALFOUNDARIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.
Public/Granted literature
- US20140258960A1 INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS Public/Granted day:2014-09-11
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