Invention Grant
- Patent Title: Apparatus and method for integration of through substrate vias
- Patent Title (中): 通过衬底通孔整合的装置和方法
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Application No.: US13445636Application Date: 2012-04-12
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Publication No.: US08969200B2Publication Date: 2015-03-03
- Inventor: Jeremiah Hebding , Megha Rao , Colin McDonough , Matthew Smalley , Douglas Duane Coolbaugh , Joseph Piccirillo, Jr. , Stephen G. Bennett , Michael Liehr , Daniel Pascual
- Applicant: Jeremiah Hebding , Megha Rao , Colin McDonough , Matthew Smalley , Douglas Duane Coolbaugh , Joseph Piccirillo, Jr. , Stephen G. Bennett , Michael Liehr , Daniel Pascual
- Applicant Address: US NY Albany
- Assignee: The Research Foundation of State University of New York
- Current Assignee: The Research Foundation of State University of New York
- Current Assignee Address: US NY Albany
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.
Public/Granted literature
- US20130270711A1 APPARATUS AND METHOD FOR INTEGRATION OF THROUGH SUBSTRATE VIAS Public/Granted day:2013-10-17
Information query
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