Invention Grant
- Patent Title: Transistor-based apparatuses, systems and methods
- Patent Title (中): 基于晶体管的设备，系统和方法
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Application No.: US13774216Application Date: 2013-02-22
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Publication No.: US08969924B2Publication Date: 2015-03-03
- Inventor: Ashish Pal , Aneesh Nainani , Krishna Chandra Saraswat
- Applicant: The Board of Trustees of the Leland Stanford Junior University
- Applicant Address: US CA Palo Alto
- Assignee: The Board of Trustees of the Leland Stanford Junior University
- Current Assignee: The Board of Trustees of the Leland Stanford Junior University
- Current Assignee Address: US CA Palo Alto
- Agency: Crawford Maunu PLLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L27/108 ; H01L29/778 ; H01L29/786 ; H01L21/84 ; H01L27/12 ; H01L29/267
Abstract:
Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
Public/Granted literature
- US20130307025A1 TRANSISTOR-BASED APPARATUSES, SYSTEMS AND METHODS Public/Granted day:2013-11-21
Information query
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