Invention Grant
US08969940B1 Method of gate strapping in split-gate memory cell with inlaid gate
有权
带嵌入门的分闸门存储单元中栅极贴片的方法
- Patent Title: Method of gate strapping in split-gate memory cell with inlaid gate
- Patent Title (中): 带嵌入门的分闸门存储单元中栅极贴片的方法
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Application No.: US14048570Application Date: 2013-10-08
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Publication No.: US08969940B1Publication Date: 2015-03-03
- Inventor: Jane A Yater , Cheong Min Hong , Sung-Taeg Kang , Asanga H Perera
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Terrile, Cannatti, Chambers & Holland, LLP
- Agent Michael Rocco Cannatti
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/788 ; H01L21/8238 ; H01L27/115
Abstract:
A process integration is disclosed for fabricating non-volatile memory (NVM) cells having patterned select gates (211, 213), charge storage layers (219), inlaid control gates (223, 224), and inlaid control gate contact regions (228).
Information query
IPC分类:
