- Patent Title: High threshold voltage NMOS transistors for low power IC technology
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Application No.: US12727312Application Date: 2010-03-19
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Publication No.: US08969969B2Publication Date: 2015-03-03
- Inventor: Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
- Applicant: Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Whitham, Curtis, Christofferson & Cook, P.C.
- Agent Joseph P. Abate
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8234 ; H01L21/8238

Abstract:
Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
Public/Granted literature
- US20100237425A1 High Threshold Voltage NMOS Transistors For Low Power IC Technology Public/Granted day:2010-09-23
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