Invention Grant
US08970052B2 Semiconductor device stack with bonding layer and wire retaining member
有权
具有接合层和电线保持构件的半导体器件堆叠
- Patent Title: Semiconductor device stack with bonding layer and wire retaining member
- Patent Title (中): 具有接合层和电线保持构件的半导体器件堆叠
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Application No.: US14049915Application Date: 2013-10-09
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Publication No.: US08970052B2Publication Date: 2015-03-03
- Inventor: Yu Hasegawa , Mitsuaki Katagiri , Satoshi Isa , Ken Iwakura , Dai Sasaki
- Applicant: PS4 Luxco S.a.r.l.
- Applicant Address: LU Luxembourg
- Assignee: PS4 Luxco S.a.r.l.
- Current Assignee: PS4 Luxco S.a.r.l.
- Current Assignee Address: LU Luxembourg
- Agency: Foley & Lardner LLP
- Priority: JP2009-019564 20090130; JP2009-270146 20091127
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L25/065 ; H01L23/00

Abstract:
In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.
Public/Granted literature
- US20140035166A1 SEMICONDUCTOR DEVICE STACK WITH BONDING LAYER AND WIRE RETAINING MEMBER Public/Granted day:2014-02-06
Information query
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