Invention Grant
US08970267B2 Asynchronous clock dividers to reduce on-chip variations of clock timing
有权
异步时钟分频器可减少片上时钟时钟变化
- Patent Title: Asynchronous clock dividers to reduce on-chip variations of clock timing
- Patent Title (中): 异步时钟分频器可减少片上时钟时钟变化
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Application No.: US12874627Application Date: 2010-09-02
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Publication No.: US08970267B2Publication Date: 2015-03-03
- Inventor: Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian
- Applicant: Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frederick J. Telecky, Jr.
- Main IPC: H03K21/00
- IPC: H03K21/00 ; H03K23/00 ; H03K25/00 ; H03K23/42
Abstract:
This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.
Public/Granted literature
- US20130176060A1 Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing Public/Granted day:2013-07-11
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