A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state.