A memory system includes a multi-port memory having a first port and a second port. First registers and second registers provide first and second addresses, respectively, to the first and second ports. An access controller controls the multi-port memory to launch an access for the valid address provided by the first input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the first clock and to launch an access for the valid address provided by the second input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the second clock.