Invention Grant
US08971718B2 Down-sampling clock and data recovery circuit having selectable rate and phase output and method of operation thereof
有权
具有可选速率和相位输出的下采样时钟和数据恢复电路及其操作方法
- Patent Title: Down-sampling clock and data recovery circuit having selectable rate and phase output and method of operation thereof
- Patent Title (中): 具有可选速率和相位输出的下采样时钟和数据恢复电路及其操作方法
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Application No.: US13486552Application Date: 2012-06-01
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Publication No.: US08971718B2Publication Date: 2015-03-03
- Inventor: Hungkei Chow , Dusan Suvakovic , Christophe Van Praet , Guy Torfs , Xin Yin , Zhisheng Li
- Applicant: Hungkei Chow , Dusan Suvakovic , Christophe Van Praet , Guy Torfs , Xin Yin , Zhisheng Li
- Applicant Address: FR Boulogne-Billancourt
- Assignee: Alcatel Lucent
- Current Assignee: Alcatel Lucent
- Current Assignee Address: FR Boulogne-Billancourt
- Agency: Hitt Gaines, PC
- Main IPC: H04B10/00
- IPC: H04B10/00 ; H04L7/033 ; H03L7/08 ; H04L25/06 ; H03L7/087
Abstract:
A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.
Public/Granted literature
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