The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.