Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.