Invention Grant
US08972810B2 I/O circuitry free of test clock coupled with destination/source circuitry 有权
I / O电路没有测试时钟与目的地/源电路耦合

I/O circuitry free of test clock coupled with destination/source circuitry
Abstract:
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
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