Invention Grant
- Patent Title: Planarization process for semiconductor device fabrication
- Patent Title (中): 半导体器件制造的平面化过程
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Application No.: US13275962Application Date: 2011-10-18
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Publication No.: US08975179B2Publication Date: 2015-03-10
- Inventor: Che-Hao Tu , Weilun Hong , Ying-Tsung Chen , Liang-Guang Chen
- Applicant: Che-Hao Tu , Weilun Hong , Ying-Tsung Chen , Liang-Guang Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/3105 ; H01L29/66 ; H01L21/28 ; H01L29/51

Abstract:
The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.
Public/Granted literature
- US20130095644A1 PLANARIZATION PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION Public/Granted day:2013-04-18
Information query
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