Invention Grant
US08975186B2 Double patterning methods and structures 有权
双重图案化方法和结构

Double patterning methods and structures
Abstract:
Various embodiments provide double patterning methods and structures. In an exemplary method, a to-be-etched layer can be provided. A stress layer can be formed on the to-be-etched layer. The stress layer can have a tensile stress. A plurality of discrete sacrificial layers can be formed on the stress layer. A sidewall-spacer material layer covering the plurality of sacrificial layers and the stress layer can be formed. The sidewall-spacer material layer can be etched to form a sidewall spacer on a sidewall of each sacrificial layer of the plurality of sacrificial layers. The stress layer at each side of the each sacrificial layer can be etched to form a groove passing through a thickness of the stress layer. The plurality of sacrificial layers can be removed.
Public/Granted literature
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IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件;其他类目中不包括的电固体器件(使用半导体器件的测量入G01;一般电阻器入H01C;磁体、电感器、变压器入H01F;一般电容器入H01G;电解型器件入H01G9/00;电池组、蓄电池入H01M;波导管、谐振器或波导型线路入H01P;线路连接器、汇流器入H01R;受激发射器件入H01S;机电谐振器入H03H;扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R;一般电光源入H05B;印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K;在具有特殊应用的电路中使用的半导体器件见应用相关的小类)
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02 .半导体器件或其部件的制造或处理
H01L21/04 ..至少具有一个跃变势垒或表面势垒的器件,例如PN结、耗尽层、载体集结层
H01L21/18 ...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体,如掺杂材料
H01L21/30 ....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的(在半导体材料上制作电极的入H01L21/28)
H01L21/31 .....在半导体材料上形成绝缘层的,例如用于掩膜的或应用光刻技术的(密封层入H01L21/56);以及这些层的后处理;这些层的材料的选择
H01L21/3105 ......后处理
H01L21/311 .......绝缘层的刻蚀
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