Invention Grant
- Patent Title: CMOS time delay and integration image sensor
- Patent Title (中): CMOS时间延迟和集成图像传感器
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Application No.: US13592419Application Date: 2012-08-23
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Publication No.: US08975570B2Publication Date: 2015-03-10
- Inventor: Naser Faramarzpour , Matthias Egbert Sonder
- Applicant: Naser Faramarzpour , Matthias Egbert Sonder
- Applicant Address: CA Waterloo
- Assignee: Teledyne Dalsa Inc.
- Current Assignee: Teledyne Dalsa Inc.
- Current Assignee Address: CA Waterloo
- Agency: Gowling Lafleur Henderson LLP
- Main IPC: H01L27/146
- IPC: H01L27/146

Abstract:
A CMOS time delay and integration image sensor is disclosed having analog sampling stages coupled to the column bus that correspond to a pixel in the column. The analog sampling stages have a first memory element that stores the pixels reset level signal and a second memory element that stores an output signal of a previous analog sampling stage in the column. The analog sampling stage integrates the signal of the previous analog sampling stage with the sampled photosignal of the corresponding pixel and subtracts the reset level. The analog sampling stage architecture provides global shuttering and correlated double sampling and only requires a single analog to digital conversion for each TDI line time.
Public/Granted literature
- US20140054443A1 CMOS TIME DELAY AND INTEGRATION IMAGE SENSOR Public/Granted day:2014-02-27
Information query
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