Invention Grant
US08975704B2 Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
有权
在28nm低功率/高性能技术上的PMOS器件的中间原位掺杂SiGe结，使用硅氧化物封装，早期晕圈和延伸注入
- Patent Title: Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
- Patent Title (中): 在28nm低功率/高性能技术上的PMOS器件的中间原位掺杂SiGe结，使用硅氧化物封装，早期晕圈和延伸注入
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Application No.: US14196517Application Date: 2014-03-04
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Publication No.: US08975704B2Publication Date: 2015-03-10
- Inventor: Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Current Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L27/092 ; H01L29/66 ; H01L29/78 ; H01L29/08 ; H01L29/10 ; H01L29/165 ; H01L21/8238 ; H01L27/088 ; H01L29/49 ; H01L29/51
Abstract:
A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
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