Invention Grant
- Patent Title: Bias circuit and method of manufacturing the same
- Patent Title (中): 偏置电路及其制造方法
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Application No.: US13129344Application Date: 2009-12-01
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Publication No.: US08975725B2Publication Date: 2015-03-10
- Inventor: Yasuhiro Hamada , Shuya Kishimoto , Kenichi Maruhashi
- Applicant: Yasuhiro Hamada , Shuya Kishimoto , Kenichi Maruhashi
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2008-309555 20081204
- International Application: PCT/JP2009/006517 WO 20091201
- International Announcement: WO2010/064412 WO 20100610
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L23/522 ; H01L23/66 ; H03F1/30 ; H03F3/195 ; H01L27/06
Abstract:
A bias circuit according to the present invention includes a resistor layer 2 which is placed above a substrate 1 and connected to a ground potential, and a conductor 4 for forming an inductor 5 placed above the resistor layer 2. Further, a manufacturing method of the bias circuit according to the present invention generates the resistor layer 2 above the substrate 1 and is connected to the ground potential, and generates the conductor 4 for forming the inductor 5 above the resistor layer 2. The present invention can provide a bias circuit and a manufacturing method of the bias circuit that enables easy integration on a semiconductor substrate and prevents parasitic oscillation.
Public/Granted literature
- US20110221032A1 BIAS CIRCUIT AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2011-09-15
Information query
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