Invention Grant
US08975736B2 Wafer level package, chip size package device and method of manufacturing wafer level package
有权
晶圆级封装，芯片尺寸封装器件及晶圆级封装的制造方法
- Patent Title: Wafer level package, chip size package device and method of manufacturing wafer level package
- Patent Title (中): 晶圆级封装，芯片尺寸封装器件及晶圆级封装的制造方法
-
Application No.: US14000111Application Date: 2011-03-16
-
Publication No.: US08975736B2Publication Date: 2015-03-10
- Inventor: Toshiaki Okuno , Katsuyuki Inoue , Takeshi Fujiwara , Tomonori Seki
- Applicant: Toshiaki Okuno , Katsuyuki Inoue , Takeshi Fujiwara , Tomonori Seki
- Applicant Address: JP Kyoto
- Assignee: OMRON Corporation
- Current Assignee: OMRON Corporation
- Current Assignee Address: JP Kyoto
- Agency: Osha Liang LLP
- Priority: JP2011-031328 20110216
- International Application: PCT/JP2011/056237 WO 20110316
- International Announcement: WO2012/111174 WO 20120823
- Main IPC: H01L23/06
- IPC: H01L23/06 ; H01L21/78 ; H01L21/50 ; H01L23/10 ; B81C1/00
Abstract:
A wafer level package has a first wafer having a plurality of chips mounted or formed thereon in a plane, and a second wafer that is opposed to the first wafer. The first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween. A gap is formed between the seal frames of the chips adjacent to each other. A partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other.
Public/Granted literature
- US20140008779A1 WAFER LEVEL PACKAGE, CHIP SIZE PACKAGE DEVICE AND METHOD OF MANUFACTURING WAFER LEVEL PACKAGE Public/Granted day:2014-01-09
Information query
IPC分类:
