A comparator used in a clock signal generation circuit compares two input signals and generates an output signal. The comparator has first and second input transistors coupled to the input signals. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. The comparator is operable in a first mode or a second mode based on a hysteresis enable signal. In the first mode the comparator applies hysteresis to the comparison of the input signals and in the second mode, compares the input signals without hysteresis.