Invention Grant
US08975952B2 CMOS logic circuit using passive internal body tie bias 有权
CMOS逻辑电路采用被动内部机身引线偏置

CMOS logic circuit using passive internal body tie bias
Abstract:
This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
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