Invention Grant
- Patent Title: CMOS logic circuit using passive internal body tie bias
- Patent Title (中): CMOS逻辑电路采用被动内部机身引线偏置
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Application No.: US13675828Application Date: 2012-11-13
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Publication No.: US08975952B2Publication Date: 2015-03-10
- Inventor: Paul S. Fechner , Weston Roper , James D. Seefeldt
- Applicant: Honeywell International Inc.
- Applicant Address: US NJ Morristown
- Assignee: Honeywell International Inc.
- Current Assignee: Honeywell International Inc.
- Current Assignee Address: US NJ Morristown
- Agency: Shumaker & Sieffert, P.A.
- Main IPC: H03K3/01
- IPC: H03K3/01 ; H03K19/094

Abstract:
This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
Public/Granted literature
- US20140132306A1 CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS Public/Granted day:2014-05-15
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