In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics.