Invention Grant
- Patent Title: Semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件
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Application No.: US13910507Application Date: 2013-06-05
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Publication No.: US08976608B2Publication Date: 2015-03-10
- Inventor: Goichi Ono , Yusuke Kanno , Akira Kotabe
- Applicant: Hitachi, Ltd.
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2012-127729 20120605
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C8/08 ; G11C29/50 ; G11C11/41 ; G11C29/12

Abstract:
A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.
Public/Granted literature
- US20130322188A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2013-12-05
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