Invention Grant
US08976855B2 Power and area efficient receiver equalization architecture with relaxed DFE timing constraint
有权
功率和面积有效的接收机均衡架构，具有轻松的DFE时序约束
- Patent Title: Power and area efficient receiver equalization architecture with relaxed DFE timing constraint
- Patent Title (中): 功率和面积有效的接收机均衡架构，具有轻松的DFE时序约束
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Application No.: US13830244Application Date: 2013-03-14
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Publication No.: US08976855B2Publication Date: 2015-03-10
- Inventor: Mingming Xu , Stefano Giacconi
- Applicant: Mingming Xu , Stefano Giacconi
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H03H7/30
- IPC: H03H7/30 ; H03H7/40 ; H03K5/159 ; H04L25/03
Abstract:
An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).
Public/Granted literature
- US20140269889A1 POWER AND AREA EFFICIENT RECEIVER EQUALIZATION ARCHITECTURE WITH RELAXED DFE TIMING CONSTRAINT Public/Granted day:2014-09-18
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