Invention Grant
US08977820B2 Handling of hard errors in a cache of a data processing apparatus
有权
处理数据处理装置的高速缓存中的硬错误
- Patent Title: Handling of hard errors in a cache of a data processing apparatus
- Patent Title (中): 处理数据处理装置的高速缓存中的硬错误
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Application No.: US12004476Application Date: 2007-12-21
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Publication No.: US08977820B2Publication Date: 2015-03-10
- Inventor: Antony John Penton , Alex James Waugh , Andrew Christopher Rose , Paul Stanley Hughes
- Applicant: Antony John Penton , Alex James Waugh , Andrew Christopher Rose , Paul Stanley Hughes
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F11/10 ; G11C29/42 ; G11C29/00 ; G11C15/00 ; G11C29/04

Abstract:
A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. Cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of an error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. A clean and invalidate operation is performed in respect of the specific cache line, and the access request is then re-performed. Cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from a lookup procedure.
Public/Granted literature
- US20090164727A1 Handling of hard errors in a cache of a data processing apparatus Public/Granted day:2009-06-25
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