Invention Grant
- Patent Title: Thread optimized multiprocessor architecture
- Patent Title (中): 线程优化的多处理器架构
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Application No.: US11702979Application Date: 2007-02-05
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Publication No.: US08977836B2Publication Date: 2015-03-10
- Inventor: Russell H. Fish, III
- Applicant: Russell H. Fish, III
- Agent Carl F. Melito
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30 ; G06F9/32 ; G06F12/08 ; G06F15/78
Abstract:
In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein each of the processors comprises local caches dedicated to each of at least three specific registers in the processor. In another aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors, wherein each of the processors is operable to process an instruction set optimized for thread-level parallel processing.
Public/Granted literature
- US20070192568A1 Thread optimized multiprocessor architecture Public/Granted day:2007-08-16
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