Invention Grant
US08987008B2 Integrated circuit layout and method with double patterning 有权
具有双重图案化的集成电路布局和方法

Integrated circuit layout and method with double patterning
Abstract:
The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
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