Invention Grant
- Patent Title: Integrated circuit layout and method with double patterning
- Patent Title (中): 具有双重图案化的集成电路布局和方法
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Application No.: US13971363Application Date: 2013-08-20
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Publication No.: US08987008B2Publication Date: 2015-03-24
- Inventor: Ming-Feng Shieh , Ru-Gun Liu , Hung-Chang Hsieh , Tsai-Sheng Gau , Yao-Ching Ku
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/308 ; H01L21/66

Abstract:
The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
Public/Granted literature
- US20150056724A1 INTEGRATED CIRCUIT LAYOUT AND METHOD WITH DOUBLE PATTERNING Public/Granted day:2015-02-26
Information query
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