Invention Grant
US08987064B2 Integrated circuit packaging system with molded grid-array mechanism and method of manufacture thereof
有权
具有模制网格阵列机构的集成电路封装系统及其制造方法
- Patent Title: Integrated circuit packaging system with molded grid-array mechanism and method of manufacture thereof
- Patent Title (中): 具有模制网格阵列机构的集成电路封装系统及其制造方法
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Application No.: US13740151Application Date: 2013-01-11
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Publication No.: US08987064B2Publication Date: 2015-03-24
- Inventor: Byung Tai Do , Arnel Senosa Trasporto , Linda Pei Ee Chua
- Applicant: Byung Tai Do , Arnel Senosa Trasporto , Linda Pei Ee Chua
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/48 ; H01L21/56 ; H01L23/495 ; H01L21/48
Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.
Public/Granted literature
- US20140197548A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2014-07-17
Information query
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