Invention Grant
- Patent Title: Method of manufacturing a three dimensional array having buried word lines of different heights and widths
- Patent Title (中): 制造具有不同高度和宽度的掩埋字线的三维阵列的方法
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Application No.: US13789930Application Date: 2013-03-08
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Publication No.: US08987111B2Publication Date: 2015-03-24
- Inventor: Jay-Bok Choi , Jiyoung Kim , Hyun-Woo Chung , Sungkwan Choi , Yoosang Hwang
- Applicant: Jay-Bok Choi , Jiyoung Kim , Hyun-Woo Chung , Sungkwan Choi , Yoosang Hwang
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2012-0032928 20120330
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/762 ; H01L21/308 ; H01L27/108
Abstract:
According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.
Public/Granted literature
- US20130260531A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2013-10-03
Information query
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