Invention Grant
US08990506B2 Replacing cache lines in a cache memory based at least in part on cache coherency state information
有权
至少部分地基于高速缓存一致性状态信息来替换缓存存储器中的高速缓存行
- Patent Title: Replacing cache lines in a cache memory based at least in part on cache coherency state information
- Patent Title (中): 至少部分地基于高速缓存一致性状态信息来替换缓存存储器中的高速缓存行
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Application No.: US12639191Application Date: 2009-12-16
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Publication No.: US08990506B2Publication Date: 2015-03-24
- Inventor: Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
- Applicant: Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/12 ; G06F12/08
Abstract:
In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.
Public/Granted literature
- US20110145506A1 Replacing Cache Lines In A Cache Memory Public/Granted day:2011-06-16
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