Invention Grant
US08995500B2 Asynchronous correlation circuit, asynchronous full adder circuit, calculation device, correlation device, asynchronous maximum value N detection circuit, and satellite signal acquisition device 有权
异步相关电路,异步全加电路,计算装置,相关装置,异步最大值N检测电路和卫星信号采集装置

  • Patent Title: Asynchronous correlation circuit, asynchronous full adder circuit, calculation device, correlation device, asynchronous maximum value N detection circuit, and satellite signal acquisition device
  • Patent Title (中): 异步相关电路,异步全加电路,计算装置,相关装置,异步最大值N检测电路和卫星信号采集装置
  • Application No.: US13944346
    Application Date: 2013-07-17
  • Publication No.: US08995500B2
    Publication Date: 2015-03-31
  • Inventor: Nobuo Karaki
  • Applicant: Seiko Epson Corporation
  • Applicant Address: JP
  • Assignee: Seiko Epson Corporation
  • Current Assignee: Seiko Epson Corporation
  • Current Assignee Address: JP
  • Agency: Harness, Dickey & Pierce, P.L.C.
  • Priority: JP2012-160507 20120719; JP2012-160508 20120719; JP2012-160509 20120719
  • Main IPC: H04B1/00
  • IPC: H04B1/00 G01S19/30
Asynchronous correlation circuit, asynchronous full adder circuit, calculation device, correlation device, asynchronous maximum value N detection circuit, and satellite signal acquisition device
Abstract:
An asynchronous correlation circuit includes a first data supply unit that dual-rail-encodes first sequence data and supplies first data to be provided for next calculation at each time when calculation is completed, a second data supply unit that dual-rail-encodes second sequence data and supplies second data to be provided for next calculation at each time when calculation is completed, an addition result storage unit, a third dual-rail encoding unit that dual-rail-encodes a storage value of the addition result storage unit, an asynchronous full addition unit that adds an output value from the first data supply unit to an output value of the third dual-rail encoding unit with a sign in response to an output value from the second data supply unit, and outputs the value, and a dual-rail decoding unit that decodes and outputs an output value of the asynchronous full addition unit to the addition result storage unit.
Information query
Patent Agency Ranking
0/0